Ultrasound photoreceivers which function in the serial 100 Gbit/s data rate range and are designed for d.c. voltage coupling to subsequent electronic circuits, e.g. to a demultiplexer circuit, in the simplest case consist of a pin photodiode with a rear-side bias feed, but also of a pin photodiode, integrated with a travelling wave amplifier TWA. The photoreceivers are usually designed as optoelectronic, integrated circuits (OEIC) which are connected to a further integrated circuit, e.g. to the demultiplexer which is mentioned above. However, subsequent electronics may also be a sampling circuit of a sampling oscilloscope or a travelling wave amplifier or likewise. A demultiplexer is hereinafter selected as subsequent electronics for explanation.
The photoreceiver converts an optical data flow which is coupled via a glass fiber into the photodiode of the OEIC, into an electrical output signal of the same data rate, which as a high-frequency output signal is transferred further to the subsequently connected demultiplexer. This demultiplexes, for example here the 100 Gbit/s electrical data signal, into two 50 Gbit/s data signals which appear at its two outputs.
If the photoreceiver is designed as a pinTWA photoreceiver according to FIG. 1, the travelling wave amplifier on the chip is integrated with the photodiode PD and its wiring to a bias resistance Rbias and a blocking capacitance Cbias, so that the photodiode signal is already amplified on the chip. The travelling wave amplifier comprises a plurality of transistors which are connected in parallel, FETS in the present case, but also bipolar transistors are possible, whose gate and drain terminals are each connected via micro-strip conductors to coplanar waveguide elements CPW. One end of the chain of coplanar waveguide elements CPW which is connected to the gate connections of the transistors via the microstrip conductor elements MSL, is connected to the photodiode PD, and the other end is connected via a terminal resistance Rgt to the negative operating voltage −Vss or via a blocking capacitance Cgt to ground or earth also with regard to RF technology. A further chain of waveguide elements CPW which is connected to the drain connections of the FETs T, on the one hand is connected to the integrated drain terminal resistance Rdt and via a chip-external bond wire inductance Ldt to a positive voltage supply connection +Vdt, and on the other hand to the signal output, to which a demultiplexer is connected for example. The pinTWA chip is supplied with voltage/current at the positive terminal +Vdt and at a negative terminal Vss (negative bias). A d.c. voltage potential Va is present at the output of the photoreceiver, apart from the high-frequency output signal or input signal for the demultiplexer, and is likewise present at the electric input of the demultiplexer. The demultiplexer in many cases has the best switching behavior if the average d.c. input voltage lies around 0 V, wherein its maximal voltage swing is to lie in a safe working range of −0.6 V to +0.4 V.
According to the state of the art, the demultiplexer circuits at their output are extremely sensitive to overvoltages, since with the high switching frequencies, the sensitive input transistors may hardly be provided with protective circuits against voltage peaks which would immediately reduce the limiting frequency. Accordingly, the user who connects a photoreceiver OEIC in series in front of the demultiplexer IC must ensure that such voltage peaks and also possible DC-offsets remain within the mentioned windows, otherwise one must reckon with a defect of the demultiplexer. The photoreceiver, in particular the pinTWA photoreceiver and the demultiplexer ICs in the high Gbit/range are currently very expensive circuits.
The output of the photoreceiver which in the case of a pinTWA photoreceiver may also be present in cascode circuitry, must therefore be connected to the input of the demultiplexer IC. With the pinTWA photoreceiver, whose potential of the high-frequency electric output may be set to around 0 V via a suitable setting of the two supply voltages +Vdt and −Vss, in practical operation, it is a question of being able to measure the voltage potential at the output of the photoreceiver, or at the input of the demultiplexer, in order to keep the supply voltages of the pinTWA photoreceiver always within the voltage margins of a secure operating range of the demultiplexer, also in the dynamic case of switching on and off as well as in operation, so as to avoid the possible destruction of the demultiplexer.
In the case of a simple photoreceiver in the form of a photodiode chip, although one or more bias terminals are provided, which permit the application of a bias voltage to the diode, in this simplified embodiment however, with a d.c. coupling of the signal-RF-output of the diode to the multiplexer circuit, the average photocurrent from the diode would lead to a shifting of the operating point of the demultiplexer, as a rule in the positive direction, by which means one departs from the optimal operating region of the demultiplexer.
With regard to the pinTWA photoreceiver, a concerted manual run-up of the two supply voltages Vdt and −Vss would have to be effected under the condition that the RF output of the photoreceiver is constantly kept around 0 V, in order to avoid the mentioned disadvantages. In order to rule out all risks of transient overvoltage impulses and also to be able to measure the output potential of the photoreceiver, the intermediate connection of a so-called bias-T into the connection line between the photoreceiver and the demultiplexer has established itself and this comprises a capacitance lying in the signal line, and a resistance or an inductance, which lead to a setting terminal. Such an application of a bias-T is also known with a pure pin-photoreceiver. These bias-Ts must be suitable for limiting frequencies in the 100 GHz region and also for lower limiting frequencies down to at least 100 KHz, in order with this to transmit the signal bandwidth as well as the so-called frame clock which may reach down to the 10 KHz range. They are thereby likewise very inexpensive and moreover they damp the high-frequency output signal of the photoreceiver by about 2 dB and thus negate a part of its amplification (10 dB).
If in prior stages of development, both components—the photoreceiver and demultiplexer are present in separate housings, then the intermediate connection of a bias-T is easily possible, even if having the previously mentioned disadvantages. In advanced housing scenarios, in the so-called co-packaging, however both components, the photoreceiver and demultiplexer are incorporated into a single housing, in order on the one hand to save housing costs and on the other hand to also reduce the signal damping between both integrated circuits, which otherwise additionally result by way of the necessary RF connection plug and leads which lie at approx. 2 dB per housing. Moreover, in this preferred co-packaging design, only medium-frequency signals leave the housing, so that connection costs for highest frequency plugs are saved. If this preferred co-packaging case is present, then both integrated circuits are packaged together in an as compact as possible manner in a housing and directly connected with ultra-short bond wires, so that then however one may no longer introduce any more bias-Ts. With this, the operationally accompanying possibility of measuring the output d.c. voltage Va of the photo receiver or the input voltage of the demultiplexer is then negated.